1. Field of the Invention
The present invention relates to a dynamic random access memory and more particularly, to a MOS dynamic random access memory (referred to hereinbelow as a MOSDRAM).
2. Description of the Related Art
The degree of integration of the MOSDRAM referred to above has been improved four times in the recent three years, with each cell becoming more and more minute and compact in size. Meanwhile, in order to secure high reliability of such memory cell reduced in size, the present applicant has designed a new kind of memory cell for storing 2-bit data by two access transistors and one capacitor, which is disclosed in detail in U.S. patent application Ser. No. 07/455,989 filed Dec. 22, 1989, now abandoned and entitled "Dynamic Semiconductor Memory Device" which corresponds to two Japanese Patent applications (Japanese Patent Application Nos. 63-330970 and 1-68880).
Referring to FIGS. 1 and 2, the above-discussed memory cell used in the MOSDRAM is shown, in which FIG. 1 shows a plane view, and FIG. 2 shows a cross-sectional view taken along a line II--II shown in FIG. 1.
The memory cell 10 includes two access transistors 12 and 13, and a memory capacitor 11, which are connected in series as shown in FIG. 3. The first access transistor 12 is formed by a gate 12a, an N+ diffusion area 12b as a source (or a drain) and another N+ diffusion area 12c as a drain (or a source). The second access transistor 13 is formed by a gate 13a, an N+ diffusion area 13b as a source (or a drain) and another N+ diffusion area 13c as a drain (or a source). The memory capacitor 11 has a lower electrode defined by an N+ diffusion area 11a which is in common with the N+ diffusion area 12b of the first transistor 12, and an upper electrode 11b defined by a polysilicon film layer 21.
A connecting hole 22 connects the drain of the transistor 13 with the upper electrode 21 of the capacitor 11. Reference WL represents a word line (a first polysilicon film layer) and references BL and BL indicate bit lines (metal films) which will be used for storing data in the capacitor 11.
The MOSDRAM employing the above described memory cell 10, which is disclosed fully in the above-mentioned U.S. Patent application, is explained hereinbelow.
In the drawings, FIG. 3 shows a circuit structure of the MOSDRAM; FIG. 4 shows waveforms of input signals; and FIGS. 5 and 6 show a waveform of potential in a bit line when data is read out.
Referring to FIG. 3, the memory cell (for 2 bits) 10 includes a memory capacitor 11, a first access transistor 12, a second access transistor 13, and storage nodes 14 and 15. The memory cell 10 is provided in association with sense amplifiers 16 and 17.
The operation, particularly of the memory cell 10 selected by the signals from a word line WLL1 and bit lines BLL1 and BLL1, is explained hereinbelow from the viewpoints of (1) reading, (2) re-writing, (3) precharging and (4) writing.